c - Non recursive makefile for manu sources directories with flat .obj directory -
i have project many sources directories. there requirement hold .obj files in 1 flat directory, e.g.
- src1
- src2
- src3
- src4
- src5
- src6
- src7
- src8
- obj
- makefile
i have list of sources files directories located in. make version 3.81 have used mixed implicit , normal rules make 3.82 cannot accomplish this. goal not use shell commands make built-in functions.
objects = $(subst .c,.o,$(srcs)) objects_obj = $(patsubst %.c,$(obj_dir)/%.o,$(notdir $(srcs))) srcdir = $(dir $(srcs)) vpath %.c $(srcdir) ... $(obj_dir) $(obj_dir)/%.o : %.c @echo "=======================================================================" @echo "compilation:" $< " --> " $@ @echo "=======================================================================" @mkdir -p $(dir $@) $(cc) $(c_flags) $(incl) $< -c -o $@
where srcs list of sources files.
is possible achieve without recursive makefiles or without using shell commands.
simply include makefile create explicit dependencies:
# makefile obj_dir:=objects src_files := $(notdir $(srcs)) all: $(src_files:%.c=$(obj_dir)/%.o) tmp_srcs := $(srcs) include $(foreach dummy, $(srcs), object_rule.mk) $(obj_dir)/.sentinel: mkdir -p $(dir $@) && touch $@
the trick in combination of include statement , foreach. foreach generate many "object_rule.mk" there files listed in srcs. included makefile, object_rule.mk generates object rule corresponding source file this:
ifeq (,$(tmp_srcs)) $(error makefile requires variable tmp_srcs set) endif src_path:=$(word 1, $(tmp_srcs)) ifeq (1, $(words $(tmp_srcs))) tmp_srcs:= else tmp_srcs:=$(wordlist 2, $(words $(tmp_srcs)), $(tmp_srcs)) endif src_file:=$(notdir $(src_path)) obj_file:=$(src_file:%.c=%.o) $(obj_dir)/$(obj_file): $(src_path) $(obj_dir)/.sentinel $(cc) $(c_flags) $(incl) $< -c -o $@
note have added dependency $(obj_dir)/.sentinel correct , accurate dependencies.
this solution doesn't need hand crafted. use gnu make standard library
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