Sharing "array of arrays" between two VHDL modules -

i have problem of sharing "array of arrays" between 2 vhdl modules.

i have declared "array of arrays" in vhdl sub-module below,

type avg_log array (0 31) of std_logic_vector(19 downto 0);  signal v1 :avg_log :=(others=>others=>'0');

i want send elements of v1()() top module, have tried port & generic, got error message.

can please me?

you need define type in package, , include in both entities via use this:

library ieee; use ieee.std_logic_1164.all;  package p_avg     type avg_log array (0 31) of std_logic_vector(19 downto 0); end package p_avg;

and in entity

use work.p_avg.all; entity my_e     port(       ...       v1 : out avg_log := (others => (others => '0'));       ...     ); end entity;

and use in port map in surrounding architecture (where package has included)... there other ways, way suggest...

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